The present invention relates to a non-volatile memory device and a method for fabricating the same.
Non-volatile memory devices for performing memory operations in the absence of an electric power have attracted much attention as next-generation semiconductor memory devices. In particular, flash memory devices employing a floating gate are widely utilized in a variety of applications. In addition, metal oxide nitride oxide semiconductor (MONOS) and silicon oxide nitride oxide semiconductor (SONOS) memory devices are being developed.
Floating gate memory devices perform memory operations via potential wells. Flash electrically erasable read only memory (EEPROM), e.g., EPROM tunnel oxide (ETox), is commonly used as a floating gate memory device. Metal insulator semiconductors (MISs), such as SONOS memories, utilize a gate dielectric film having a double- or triple-layered structure to realize a charge trapping structure. The charge trapping structure includes a triple-layered stack consisting of a charge tunneling layer, a charge trapping layer and a charge blocking layer. MIS-type memory devices perform memory operations utilizing charge traps present on a dielectric film bulk, an interface between adjacent dielectric films, or an interface between a dielectric film and a semiconductor.
Flash EEPROMs include one transistor in each memory cell. MONOS or SONOS devices used as full-featured EEPROMs may include a selective transistor in addition to the cell transistor in each memory cell to execute programming and erasing operations in a byte-unit. The selective transistor selects a memory cell so that programming and erasing operations can be carried out in a byte-unit. For this reason, memory functions are substantially performed by the cell transistor. Accordingly, the cell transistor may have a SONOS structure. For example, a cell transistor includes a gate dielectric film having an oxide nitride oxide (ONO) structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are sequentially stacked on a silicon (Si) semiconductor substrate. The cell transistor may further include a control gate arranged on the gate dielectric film.
In a charge trapping structure including an ONO stack, charge trapping is mainly carried out by the silicon nitride film. The reliability of the memory device greatly depends on the thickness and film quality of the silicon nitride film. To improve the reliability of the memory device, it is preferable that the silicon nitride film has a large thickness. However, the large thickness of the film makes it difficult to adjust a threshold voltage (Vt) to a desired level and requires a high voltage and power for programming. When deterioration of the film quality of the silicon nitride film occurs due to a variation (e.g., thinness) in the thickness thereof, charge leakage increases thereby decreasing charge retention time. As a result, the reliability of the memory device deteriorates. In an attempt to solve these problems, a charge trapping structure has been suggested that employs a charge trapping layer having a multi-layered (including a double-layered) stack consisting of a silicon oxide film and a silicon nitride film, and a dielectric film having a higher dielectric constant.
The introduction of the dielectric film having a higher dielectric constant into the charge trapping layer aims to reduce a device control voltage and improve current drivability. In addition, the introduction of the high-dielectric film is advantageous in reducing sub-threshold swing thereby decreasing defect density and improving reliability of the device. For example, a stacked structure including alumina, hafnia and alumina (Al2O3/HfO2/Al2O3) in this order has been suggested.
When hafnia is deposited on alumina, sequential deposition of different kinds of oxide films involves a complicated fabrication process. In addition, an equipment structure to realize such a process is complicated, and maintenance and management for mass-production become difficult. Furthermore, these attempts involve a process for depositing an oxide film on the surface of a silicon substrate, thereby causing undesired oxidation on the surface of the silicon substrate. An amorphous silicon oxide film created by the oxidization of silicon has a low dielectric constant, as compared to alumina or hafnia, thereby causing an increase in the thickness of an equivalent oxide film of a charge tunneling layer in a charge trapping structure.
Accordingly, attempts have been made to develop non-volatile memory semiconductor devices capable of exhibiting prolonged data retention time, high processing speed and low driving voltage using simple methods, as compared to ONO structures.